1. Field of the invention -- The present invention pertains to monocrystalline three-dimensional integrated devices, and more particularly, pertains to devices containing a 3-D doping pattern forming varied devices and circuits that may be junction-isolated and with interconnecting signal paths and power buses, that also may be junction-isolated, and that may have tunnel junctions connecting N-type to P-type regions.
The present invention also pertains to use of a thin monocrystalline lattice-matched silicide layer as an ohmic contact and/or a thicker such silicide region as a conductor. The monocrystalline devices can also be surrounded by an insulator.
2. Description of the Prior Art -- The prior art, such as stacked CMOS, has been concerned with patterning and contouring various materials on the surfaces of semiconductor wafers by using a variety of techniques as a means of achieving more than one layer of circuitry on a substrate.
Prior work in three dimensions has been applied mainly to stacked devices, mostly CMOS, and circuits achieved by complex but largely conventional technologies. The motivation was to have the convenience of insulators for isolation and metals for electrical conduction while taking limited advantage of the third dimension. Numerous problems remain. First, there are reliability penalties because of the interfaces involved. Second and third, there are additional reliability and yield penalties connected with the necessary in-process storage and handling. Fourth, there is the thermal-conductivity penalty. Because power dissipation is already a problem in 2-D circuitry, power dissipation is a greater problem in 3-D circuitry and must be accounted for accordingly. The prior-art stacked approach also included problems of inadequate crystalline quality and control, and inadequate planarity in the advancing free surface. Stacking of largely conventional devices has been nothing more than an evolutionary extension of the existing prior-art processes in stacking semiconductor layers separated by an insulator and involving recrystallized material.
The present invention overcomes the disadvantages of the prior art by providing a monocrystalline three-dimensional integrated circuit. At a given feature size, the 3-dimensional IC provides for greatly increased volumetric densities, as well as improved reliability. Reliability is enhanced by the elimination of interfaces between dissimilar materials. Thermal properties are improved by the exclusion of amorphous material from within the monolith. An amorphous insulator, such as silicon dioxide, has thermal conductivity one hundred times worse than that of silicon. Furthermore, a monocrystalline three-dimensional integrated circuit can be fabricated in a continuous process which minimizes the number of different processing steps and reduces turnaround time. Thin silicide regions also provide for ohmic contacts and thicker silicide layers provide for conductors. An insulator can be provided about each entire device. The silicide and insulator regions combined with semiconductor regions constitute a monocrystalline integrated circuit.